Principal Design Verification Engineer – High Performance CPU Subsystem

About this role

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

Are you ready?  

To learn more about SiFive’s phenomenal success and to see why we have won the   GSA’s prestigious Most Respected Private Company Award   (for the fourth time!), check out our   website   and   Glassdoor   pages.

Job Description:   The Role SiFive is looking for a Principal Design Verification Engineer to lead verification strategy and execution for a high-performance CPU subsystem spanning both out-of-order CPU core development and cache-coherent interconnect/subsystem behavior.

This is a Principal individual-contributor role for an engineer who can define architecture-aware verification strategy, identify risks early, solve the hardest subsystem-level problems, and raise verification quality across a broader organization.

The role bridges key CPU and uncore domains, including high-performance OoO core areas such as Frontend, Midcore, Load-Store Unit, and Hardware Prefetch, together with coherent data movement, protocol correctness, ordering, flow control, quality-of-service behavior, and subsystem integration across interconnect fabrics and bridge paths.

You will work closely with architecture, RTL, formal, performance, and design verification teams to ensure design intent is captured correctly, debugability is considered early, and signoff quality is achieved with strong technical judgment and scalable methodology.

Responsibilities • Lead verification strategy and execution for high-performance CPU subsystem development, with scope spanning OoO core microarchitecture and coherent interconnect/subsystem behavior.

• Own verification planning, execution, debug, coverage analysis, and closure from block level through subsystem integration and signoff.

• Define verification strategies for complex CPU behaviors including branch prediction, instruction fetch, issue/dispatch behavior, pipeline interactions, load/store ordering, hazard handling, memory consistency, and hardware prefetch correctness.

• Define verification strategy and closure criteria for coherent traffic, protocol correctness, ordering rules, backpressure, buffering behavior, arbitration, QoS, and error handling across cache-coherent interconnect paths.

• Drive verification across interface boundaries, bridges, and protocol adaptation paths, including conversion, buffering, and related subsystem-level data movement behavior.

• Develop high-value checkers, scoreboards, assertions, stimulus strategies, and coverage models that expose corner cases and improve bug-finding efficiency across both core and uncore verification problems.

• Apply the right verification method for the problem, using simulation, formal techniques, and emulation to improve quality, accelerate turnaround, and strengthen debug efficiency on large subsystem workloads.

• Partner with architects and designers from early feature-definition stages to review specifications, identify ambiguity, and improve designs from a verification and debugability perspective.

• Drive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.

• Mentor engineers, influence team-wide methodology, and shape reusable verification approaches that benefit future generations of high-performance CPU subsystems.

Minimum Qualifications • BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• 12+ years of relevant experience in CPU/core or SoC functional verification, with depth appropriate for a Principal / T6 role.

• Direct experience with out-of-order core verification and strong understanding of CPU microarchitecture.

• Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior, and verification of ordering and flow-control semantics.

• Deep expertise in one or more CPU areas such as Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.

• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.

• Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution.

• Strong software development, scripting, and automation skills for building scalable DV infrastructure and workflows.

Preferred Qualifications • Experience spanning both high-performance CPU core verification and coherent interconnect, cache, or memory-subsystem verification in large SoCs.

• Experience with subsystem integration, bridge-heavy designs, or protocol interactions across multiple interfaces.

• Experience using formal verification for bounded, interface-heavy, or high-risk microarchitectural problems.

• Experience using emulation to accelerate verification and improve turnaround on large CPU and subsystem verification workloads.

• Experience collaborating eff

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