Principal Design Verification Engineer – CPU Coherent Interconnect

About this role

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

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Job Description:   About the Role SiFive is looking for a Principal Design Verification Engineer to lead verification strategy and execution for a scalable cache-coherent interconnect subsystem used in high-performance CPU and SoC platforms.

This is a principal tech-lead role for an engineer who can define architecture-aware verification strategy, identify risk early, solve complex subsystem-level problems, and raise verification quality across the broader interconnect verification effort. In this role, you will work across architecture, RTL, formal, performance, and design verification teams to verify coherent data movement, protocol correctness, ordering, flow control, buffering behavior, arbitration, quality-of-service behavior, and subsystem integration across multiple interfaces and bridge paths.

Responsibilities • Lead verification planning and execution for a cache-coherent interconnect subsystem from block level through subsystem integration and signoff. • Define verification strategy, test plans, closure criteria, assertions, checkers, scoreboards, stimulus approaches, and coverage models for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, arbitration, QoS, and error handling. • Drive verification across interface boundaries, bridges, protocol adaptation layers, and related subsystem data-movement paths. • Develop high-value directed and constrained-random scenarios that expose corner cases in coherency, concurrency, credits, ordering, fairness, and performance-sensitive traffic behavior. • Partner closely with architecture, RTL, and formal teams to review specifications, close ambiguity early, and improve design debugability and verification completeness before issues harden late in the cycle. • Drive efficient root-cause analysis across specification, RTL, assertions, test content, and verification infrastructure, and push issues to durable closure. • Apply the right verification method for the problem, including simulation, formal techniques, emulation, and performance-oriented verification where appropriate. • Influence methodology and infrastructure across the broader horizontal interconnect verification effort, not just the block directly assigned to you. • Mentor engineers and raise the technical bar through reviews, debug leadership, stronger verification practices, and reusable infrastructure.

Minimum Qualifications • BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field. • 12+ years of relevant experience in CPU, subsystem, SoC, or ASIC functional verification, with depth appropriate for a Principal / T6 role. • Strong hands-on experience with SystemVerilog-based verification and reusable verification infrastructure for complex hardware subsystems. • Strong understanding of cache-coherent systems, on-chip interconnects, CPU memory-subsystem behavior, and verification of ordering, snooping, and flow-control semantics. • Deep experience creating verification plans, assertions, checkers, scoreboards, coverage models, and debug workflows for complex subsystem-level designs. • Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution. • Strong software, scripting, and automation skills in Python or similar languages for scalable DV infrastructure and workflows. • Strong technical communication and the ability to work effectively across architecture, RTL, formal, performance, and verification teams.

Preferred Qualifications • Direct experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance CPU or SoC environments. • Experience with large subsystem integration challenges involving coherent traffic, ordering, arbitration, QoS, error handling, and bridge-heavy designs. • Experience with memory consistency, weak ordering, and multicore coherency verification challenges. • Experience with formal verification, emulation, or performance-oriented verification for complex subsystem signoff problems. • Demonstrated technical leadership through mentoring engineers, influencing methodology, and driving cross-team execution on difficult verification efforts.

What Success Looks Like • Verification plans capture the real architectural and subsystem-level risks early and completely. • Difficult coherent interconnect bugs are found early, debugged efficiently, and closed with durable fixes. • Verification quality, methodology, and reusable infrastructure improve across the broader interconnect DV organization because of your contributions. • Architecture, design, and DV teams rely on this engineer as a technical

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