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Senior/Principal RF Test Engineer, Texas Institute for Electronics

The University of Texas at Austin

AUSTIN, TX | MONTOPOLIS RESEARCH CENTER, UShybrid

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About this role

Job Posting Title: Senior/Principal RF Test Engineer, Texas Institute for Electronics ---- Hiring Department: Operational Services and Strategies ---- Position Open To: All Applicants ---- Weekly Scheduled Hours: 40 ---- FLSA Status: To Be Determined at Offer ---- Earliest Start Date: Ongoing ---- Position Duration: Expected to Continue ---- Location: AUSTIN, TX ---- Job Details: General Notes  About TIE Texas Institute for Electronics (TIE) is a transformative, well-funded semiconductor foundry venture combining the agility of a startup with the scale of a national initiative.

Our Mission A key part of our mission is to advance the state of the art in 3D heterogeneous integration (3DHI), chiplet-based architectures, and multi-component microsystems- catalyzing breakthroughs across microelectronics, artificial intelligence, quantum computing, high-performance computing, and next-generation healthcare devices.

Our Impact Backed by $1.4 billion in combined funding from DARPA, Texas state initiatives, and strategic partners, we are building foundational capabilities in advanced packaging and integrated design infrastructure to restore U.S. leadership in microelectronics manufacturing.

Our Technology TIE’s 3DHI and chiplet integration platforms integrate novel thermal management and advanced interconnect solutions to deliver unprecedented performance and energy efficiency. Operating at the intersection of defense electronics and commercial markets, TIE offers a rare opportunity to reimagine an industry from the ground up and build transformative products with global impact.

Must be eligible to work in the United States on a full-time basis for any employer without sponsorship.

Purpose  The Senior/Principal RF Engineer will help ensure new technologies are evaluated and ready to move forward by providing reliable performance insights that support decision-making. They will also strengthen the organization’s testing capabilities by improving processes, building effective tools, and creating clear guidance for internal teams and partners.

Responsibilities  Senior RF Engineer • Develop and execute RF test plans for K-band (18–27 GHz), Ka-band (27–40 GHz), and W-band (75–110 GHz) microsystems at wafer, die, module, and system levels. • Perform S-parameter characterization, on-wafer probing, noise figure measurements, and power sweeps using vector network analyzers, spectrum analyzers, and signal generators. • Design and implement automated test sequences using Python, MATLAB, or LabVIEW to drive measurement instruments and collect production-grade data across process corners and temperature. • Develop de-embedding methodologies and calibration strategies for high-frequency measurements, including TRL, LRRM, and multi-line calibrations for on-wafer and package-level probing. • Correlate measured RF results against EM simulation models (HFSS, ADS, AWR, CST) to validate design intent and feed deviations back to the design and packaging teams. • Characterize passive and active RF components—including transmission lines, filters, LNAs, PAs, and T/R modules—within 3.0D heterogeneously integrated assemblies. • Support test infrastructure buildout, including fixture design, probe card specification, and lab setup for TIE’s RF characterization capabilities. • Author test reports, standard operating procedures, and design-for-test guidelines to support ecosystem partners and internal engineering teams.

Principal RF Engineer • Define and own the RF test strategy for TIE’s 3.0D heterogeneously integrated microsystems across K-band (18–27 GHz), Ka-band (27–40 GHz), and W-band (75–110 GHz), spanning wafer, die, module, and system levels. • Architect end-to-end test flows—from design-for-testability requirements through production screening—ensuring robust, repeatable, and scalable characterization of RF, mixed-signal, and antenna-in-package subsystems. • Lead development of advanced de-embedding, calibration, and measurement methodologies for novel 3DHI interconnect structures, including hybrid bonding interfaces, glass/Si interposers, and redistribution layers. • Drive test-to-model correlation across EM simulation (HFSS, ADS, AWR, CST) and measured data, establishing feedback loops with design, process, and packaging teams to accelerate yield learning and performance optimization. • Specify, procure, and commission RF test infrastructure—including probe stations, VNA configurations, automated handlers, and environmental chambers—for TIE’s characterization lab buildout. • Establish and mentor the RF test engineering team, setting technical standards, review processes, and best practices for measurement automation, data management, and statistical analysis. • Engage with foundry, EDA, metrology, and defense-program partners to define and validate test enablement requirements for next-generation RF packaging technologies. • Author test strategies, reliability qualification plans, reference test procedures, and design-for-test guidelines that become part of TIE’s Assembly Design Kit (ADK) deliverables.

Required Qualifications  Senior RF Engineer • M.S. in Electrical Engineering, Microwave Engineering, Applied Physics, or a related discipline with emphasis on RF/microwave measurement and characterization. • 5+ years of hands-on experience in RF/microwave testing, characterization, or validation of ICs, modules, or packaged systems operating at K-band frequencies and above. • Deep working knowledge of S-parameter measurement, VNA calibration techniques, de-embedding, and on-wafer probing methodologies. • Proficiency with RF test instruments (VNAs, spectrum analyzers, signal generators, power meters) and measurement automation using Python, MATLAB, or LabVIEW. • Familiarity with RF simulation tools such as Keysight ADS, Ansys HFSS, Cadence AWR, or CST Studio for test-to-model correlation. • Understanding of electromagnetic effects in advanced packaging—signal integrity, coupling, and loss across interposers

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