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PD - Sr Staff — CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology |

Eliyan

Bay Area, USonsite

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About this role

ABOUT THE ROLE As a Sr Staff / Principal CAD & Design Methodology Engineer, you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You will define and deploy multi-vendor, multi-foundry design methodology platforms, lead hierarchical SoC implementation strategies, and drive low-power chiplet products. You will own the R2G (RTL-to-GDSII) system architecture spanning Intel, TSMC, Samsung, and GlobalFoundries nodes — enabling scalable, high-quality tapeouts across diverse product classes.

Salary insight

This posting doesn't disclose pay. Across 8,589 San Francisco jobs with disclosed salaries on ForgeApply, the median is $200k.

Based on live postings with disclosed pay on ForgeApply; refreshed daily. Not an estimate of this employer's offer.

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