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Sr. Principal Product Engineer

Marvell

Santa Clara, CA, USonsite

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About this role

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell’s focus on Storage controllers and cloud data center connectivity solution enabled our customer to move data inside and between cloud data center faster and more reliably. The PAM4 DSP technology enabled 200G, 400G and 800G data transfer rate within the data centers. The Coherent DSP technology enabled 100G and 400G data transfer rate between data centers. Marvell is the enabler and partner of world’s leading cloud hyper scalers in area of transferring data from Copper PHY to the world of Optics. What You Can Expect As a Sr. Principal Product Engineer in Marvell’s AI Connectivity Group, you will lead the productization of cutting-edge datacenter connectivity solutions. You will drive new product introduction (NPI) from early silicon bring-up through mass production, while collaborating with a global team and coordinating across design, test, foundry, and reliability functions. This role requires both deep technical expertise and strong leadership to ensure successful execution across multiple concurrent programs. • Lead NPI efforts for high-speed datacenter products, including silicon bring-up, DFT validation, and test methodology development. • As a leader across multiple NPI programs, you will collaborate with global team of product engineers; providing strategic direction, hands-on technical guidance, and mentorship to drive successful NPI development. • Oversee multiple concurrent product ramps, ensuring alignment across design, test, foundry, and reliability teams in a matrixed environment. • Drive yield characterization, root cause analysis, and correlation across bench, wafer sort, and final test to meet cost and quality targets. • Lead cross-functional reviews and drive resolution of technical and operational issues impacting product readiness. • Ensure timely delivery of engineering samples to support early customer engagement and validation. • Partner with operations and supply chain to scale production capacity, qualify alternate sources, and improve manufacturing efficiency. • Champion continuous improvement initiatives in test infrastructure, data analytics, and product engineering best practices.

What We're Looking For

• M.S. or Ph.D. in Electrical/Electronics Engineering or a related field.

• 15+ years of experience in the semiconductor industry, with a strong track record in product engineering, device physics, and end to end NPI workflow.

• Deep expertise in advanced technology nodes (10nm and below), with hands-on experience in silicon bring-up, yield optimization, and test strategy.

• Proven leadership in managing cross-functional teams and mentoring engineers across regions.

• Demonstrated success in leading large-scale, multi-product development and ramp programs across global matrix organizations.

• Strong knowledge of yield analysis, quality management tools (GR&R, Cp, Cpk), and statistical data analysis.

• Proficiency with ATE concepts (e.g., Advantest 93K, UltraFlex), test handlers, and wafer probers.

• Excellent communication and stakeholder management skills, with the ability to influence across engineering, operations, and executive teams.

• Demonstrable knowledge of yield analysis, quality management tools, GR&R, Cp, Cpk.

• Self-directed, capable of managing complex projects, working individually and collaborating with other technologists to achieve objectives.

• Excellent communication skills, including written and spoken English.

Expected Base Pay Range (USD) 156,820 - 234,900, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.


This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.
 Additional Compensation and Benefit Elements   Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .

Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our inter

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