Senior Density Fill Development Engineer

About this role

Job Details:

Job Description: The Role and Impact

Join Intel's Design Technology Platform (DTP) organization and become an integral part of a highly skilled team driving the development of cutting-edge technologies. As an EDA Tools Software Engineer, you will design, develop, test, and debug software tools and methodologies that directly support Intel's hardware product design and manufacturing processes. Your work will enable design teams to innovate faster, meet complex manufacturability constraints, and deliver industry-leading products to market. By contributing to Intel's advanced process technologies, you will play a pivotal role in achieving leadership in design automation and fostering a culture of innovation.

Key Responsibilities • Design, develop, and debug Fill components of Process Design Kits (PDKs),

• Provide algorithmic solutions using tools such as Calibre, ICV, and Pegasus to address density deficiencies and ensure manufacturability compliance.

• Collaborate with process developers, design rule owners, and end users to define requirements and implement state-of-the-art solutions.

• Automate workflows to enhance efficiency, accuracy, and deployment across design teams.

• Develop comprehensive test cases and systems to validate software tools and ensure seamless integration with various design methodologies.

• Innovate and drive advancements in EDA tools and methodologies to meet the evolving needs of Intel's technology ecosystem.

• Partner with cross-functional teams and external EDA vendors to define and implement new tool features and methodologies.

• Maintain documentation, including training materials and user guides, to support customers and ensure robust deployment.

In this role, you will have a unique opportunity to make a lasting impact by enabling Intel's success in the competitive semiconductor landscape. Take the next step in your career and join a team where your expertise will help shape the future of technology innovation.

Qualifications: Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 8+ years of experience, Master's degree with 5+ years of experience, or PhD with 2+ years of experience.

• Minimum 5 years of hands-on experience with at least one industry-standard physical verification platform (Calibre, ICV, or Pegasus), including methodology development, rule deck debugging, or production deployment. 

• 3+ years of direct experience developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, or PVL/PVTCL for DRC, density, or fill verification applications.

• Solid understanding of semiconductor device physics, process technology, and design rules.

• Experience in developing algorithmic solutions for physical design challenges in advanced manufacturing nodes.   

• Strong knowledge of Unix/Linux platforms and computing environments.

Preferred Qualifications

• 5+ years of hands-on experience developing, deploying, or supporting density fill methodologies for semiconductor technologies at 16nm and below, including ownership of fill rule implementation, density compliance, or manufacturability optimization.

• Experience with advanced physical verification techniques, including DRC, and density/fill modules.  

• Industry experience with other foundry technologies in this domain is strongly desirable

• Familiarity with custom layout tools such as Cadence Virtuoso or Synopsys Custom Designer.  

• Deep understanding of technology scaling challenges and their impact on physical design rules.   

• Proven track record of collaborating across multiple internal and external teams to deliver optimal solutions.

• Exceptional analytical and problem-solving skills with the ability to address cross-disciplinary challenges.

• Strong written and verbal communication skills, with the ability to present complex technical concepts clearly.

• Leadership experience driving innovation, process improvements, or cross-functional initiatives.

• Strong preference for candidates with experience from semiconductor foundries, advanced packaging organizations (OSATs), integrated device manufacturers (IDMs), or EDA vendors, where they have contributed to physical verification, density-fill methodology development, process design kits (PDKs), or manufacturing-driven design solutions.

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, Oregon, Hillsboro

Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .     Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USD     The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.    

Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between wor

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