Senior CPU Front End Methodology Engineer

About this role

Job Details:

Job Description: About Intel Foundry Services Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.

Position Overview The Aerospace, Defense & Government (ADG) IP Enablement Application Engineer provides comprehensive technical support to Intel Foundry Services customers on IP integration challenges. This dynamic role requires a versatile engineer who engages with IP design teams and internal/external customers across all phases of IP development - from architecture through post-silicon validation and debug. The position embodies customer obsession by quickly resolving issues and providing hands-on debug across all design domains.

Key Responsibilities

IP Integration & Customer Support • Provide comprehensive technical support to Intel Foundry Services customers on IP integration issues, working independently with design teams and customers to solve complex challenges remotely or onsite • Fully own assigned IPs and work with internal and external customers to help them integrate Intel IPs into SoCs, providing expert technical support throughout the integration process • Drive resolution of customer issues related to IP collaterals generation, logic design verification, IP release, and integration in SoC environments

Cross-Functional Collaboration & IP Development • Work with cross-functional teams to develop SoC and IP integration methodologies and best practices • Engage with IP development teams to ensure all IP collaterals are generated and provided according to customer requirements and industry standards • Collaborate with internal teams across Intel and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on foundational IP integration issue resolution

Customer Requirements & Training • Engage in upfront identification and documentation of customer requirements, working with IP design teams to disposition and address requests • Prepare comprehensive customer training materials and provide training on IP architecture, specifications, and fuse/register settings to enable effective debug • Create application notes, documentation, and deliver technical training presentations to customers and internal teams

Quality & Process Improvement • Drive quality improvements in design kits and documentation, assisting in removing barriers to successful customer design tape-outs • Support debugging and problem-solving activities in collaborative team environments • Contribute to methodology improvements that enhance IP integration productivity and customer satisfaction

Core Competencies • Strong technical problem-solving and debugging capabilities • Ability to work independently and manage customer relationships effectively • Excellent communication skills for technical training and customer support • Willingness to travel to customer sites as required

Qualifications: The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates

Minimum Qualifications • US Citizenship required • Ability to obtain a US Government Security Clearance • Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study • 2+ years of experience in SOC IP Integration • 3+ years of combined experience in RTL design and DFT using Verilog/System Verilog • Experience in ASIC or SoC development

Preferred Qualifications: • Active US Government Security Clearance with a minimum of Secret level • Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study • Experience with one or more industry standard IO interfaces including (ADPLL, GPIO, Digital Thermal Sensors, DDR, LPDDR, PCIE, USB, USB TypeC, Ethernet, etc.) • Experience with VCS, Verdi, Spyglass or equivalent tools • Experience with IP integration and design flow challenges within the context of subsystems and SOCs • Experience with IP development • Experience in scripting languages like such as Perl/Tcl/ and Python

What We Offer • Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications • Direct customer engagement and technical leadership in advanced memory design • Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio • Competitive compensation • Professional development in memory design methodologies and foundry services • Direct impact on national security through advanced memory semiconductor solutions

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, Arizona, Phoenix

Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro

Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious cree

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