Product Failure Analysis Engineer

About this role

Job Details:

Job Description: About Altera At Altera™, our independence as the world’s largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry ‑ leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role We are seeking an experienced semiconductor Failure Analysis Engineer responsible for debug and root cause analysis of yield, reliability and customer returns on FPGA’s using advanced foundry process technologies.  This role requires partnering with IC and Package design, Foundry Engineering, Product and manufacturing Engineering, and Reliability teams for driving systematic fault isolation and debug.

In this role, focus will be on non-destructive electrical fault isolation by debugging electrical test responses and circuit/layout analysis.  Experience in using fault isolation using Photo Emission/Infrared microscopy (EMMI), Laser Voltage Probing (LVP) and Optical Beam Induced Resistance Change (OBIRCH) and other fault isolation tools is required.

Key Responsibilities • Collaborate with Product/Yield/Reliability Engineers to drive electrical verification, and fault isolation during product development, yield improvement and reliability risk assessments

• Support debug and fault isolation on customer returns

• Define, execute and interpret fault isolation methods as appropriate to non-destructively isolate a failure using commercial testers and fault isolation tools

• Proficient in independently using Emission microscopes, Laser Voltage Probing and OBIRCH tools

• Experienced with layout, schematic and design analysis tools

• Collaborate with physical failure analysis team on defect modes

Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$149,100 - $215,925   USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

#LI-MD1

Qualifications: Minimum Qualifications • Bachelor's degree in Electrical Eng, Materials Science, Physics, Mechanical Engineering or a related field

• 8+ years of experience in semiconductor failure analysis

• 8+ years of experience with Layout & Design tools (Virtuoso, Avalon, SysNav, etc)

• 8+ years of experience with FA tools such as Laser Voltage Probing (LVP), Photo Emission EMMI, Optical Beam Induced Resistance Change (OBIRCH)

• 8+ years of experience with DFT and logic fault localization knowledge.

• 8+ years of experience driving investigations to root-cause and to drive yield/reliability improvements.

Preferred Qualifications • 10+ years of experience in semiconductor failure analysis

• Understanding of FPGA architecture

• Understanding design debug features (DFT)

• Experience with using Teradyne Ultraflex tester

• Semiconductor packaging failure analysis.

Job Type: Regular

Shift: Shift 1 (United States of America)

Primary Location: San Jose, California, United States

Additional Locations:

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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