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Principal Signal and Power Integrity Engineer

Astera Labs

San Jose, CA, USonsiteAI

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About this role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

At Astera Labs, we seek motivated Principal Signal and Power Integrity Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations. This position will be onsite.

Basic Qualifications

• Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred.

• 8+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications.

• 8+ years of hands-on high-speed SI/PI design, simulation, and measurement experience.

• Have a proven track record with defining hardware system constraints and high-speed technology roadmaps.

• Cross-functional design mentality with the electrical design community to develop systems.

• Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic environment.

• Proven track record solving problems independently, preferably as a tech lead.

• Entrepreneurial, open-minded behavior, and can-do attitude.

• Authorized to work in the US and start immediately.

Required Experience

• Familiar with SI and PI design challenges for PCIe Gen5/6 and/or 224/448G Ethernet PCB and interconnects

• 2D and 3D EM simulation experience with Cadence/Ansys/ADS/etc. toolsets

• EM modeling of BGA and connector structures

• High-speed SERDES channel simulation, and equalization

• PI simulations with Ansys/Cadence toolsets

• Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc.

• Working knowledge of PCB fabrication limits and trade-offs

• Familiar with industry-standard such as PCI-SIG, and IEEE802.3, especially Electrical sections.

• Strong debugging, analysis, and problem-solving skills with experience leading root cause and correction action teams. An inherent sense of urgency and accountability. Must have the ability to multi-task in a fast-paced environment.

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $203,000 USD - $230,000 USD for Principal level, and $237,500 USD - $250,000 USD for Senior Principal level. The actual level is to be determined by the years of experience and interview outcome. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Salary insight

This posting doesn't disclose pay. Across 8,773 San Francisco jobs with disclosed salaries on ForgeApply, the median is $200k.

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