Principal IP Signoff & Methodology Engineer

About this role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Role Overview

Astera Labs is looking for a Principal IP Signoff & Methodology Engineer to own the readiness, quality, and signoff of internal and external IP blocks before they are released into SoC and system implementation flows. This role sits at the intersection of IP development, physical design, and tapeout execution, with responsibility for ensuring that IP deliverables from both external vendors and internal engineering teams are complete, validated, and integration-ready.

You will drive signoff closure and revision management across key IP handoff views and verification checks, including RTL, SDC, LEF/DEF, netlists, timing, physical verification, and package-aware considerations such as die and bump views. You will also drive configuration management of digital IP and ensure adherence to Astera-defined specifications, configurations, and usage profiles. The right candidate combines strong digital and physical design fundamentals with disciplined execution, debug ownership, and the ability to partner closely across digital, analog, package, CAD, and integration teams.

Key Responsibilities:

IP Release Readiness

• Own the completeness, consistency, and configuration management of all internal and external IP deliverables, including supported configurations and usage profiles.

• Own signoff readiness for IP releases, ensuring all required handoff views and collateral are complete, version-controlled, validated, and integration-ready.

• Review and validate key IP deliverables such as RTL, timing constraints (SDC), synthesized netlists, LEF/DEF, floorplan-related data, and supporting documentation.

• Define and maintain IP signoff checklists, release criteria, quality gates, and acceptance requirements for reusable IP.

• Drive alignment between IP providers and SoC or subsystem implementation teams on expected deliverables, quality metrics, and release timelines.

Digital Signoff

• Run, review, and validate digital signoff checks for IP releases, including timing, logical consistency, and implementation quality.

• Verify the completeness and correctness of RTL, timing constraints, synthesized netlists, and other digital collateral required for downstream integration.

• Ensure consistency across RTL, netlist, timing, and physical views prior to IP release.

• Analyze digital signoff issues, identify root causes, and drive closure in partnership with design, physical design, and CAD teams.

Signoff and Physical Verification

• Run, review, and debug physical verification signoff for IP and related assembly views, including DRC, LVS, PERC, and other required physical signoff checks.

• Analyze physical verification results, identify root causes, and drive closure of violations in partnership with design, layout, and CAD teams.

• Verify consistency across abstract, netlist, physical, and package-related views to support clean downstream integration.

• Assess signoff readiness not only at the block level but also in the context of top-level integration, die, and bump/package interactions where applicable.

Debug, Integration, and Risk Management

• Triage digital, physical, analog, and mixed-signal signoff issues and drive structured debug to resolution.

• Partner with IP design, physical design, CAD, packaging, and integration teams to resolve signoff issues and reduce schedule risk.

• Track signoff metrics, closure status, release readiness, and risk items, and communicate progress clearly to project stakeholders.

• Identify recurring failure modes in IP releases and improve methodology, automation, and review practices to increase first-pass success.

Methodology and Continuous Improvement

• Improve digital and physical signoff flows, checklists, and automation used to qualify IP for release.

• Standardize release content, naming conventions, validation procedures, and acceptance criteria across multiple IP types.

• Help define best practices for IP handoff into chip, package, card, and system design environments.

• Contribute to scalable signoff methodology for increasingly complex, high-performance connectivity and AI infrastructure products.

Basic Qualifications

• Strong hands-on experience with signoff views and deliverables such as RTL, SDC, LEF/DEF, synthesized netlists, timing reports, and related physical design artifacts.

• Experience defining signoff metrics, release dashboards, automation, and methodology improvements across multiple programs.

The base salary range is $175,000.00 USD – $230,000.00 USD . Your base salary will be determined based on your location, experience, and the pay of employees in similar positions We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Similar jobs

• Senior Digital Design Engineer, IP and Methodology — Asteralabs · San Jose, California, United States
• Sr. Staff Engineer, Timing Methodology & Signoff — Ambiqmicroinc · Austin, Texas, United States
• Principal Physical Design Engineer, Methodology — Asteralabs · San Jose, California, United States
• Design Verification Engineer - Internal IP — Etched · San Jose
• Design Verification Engineer - Internal IP — Etched · Austin
• Principal Digital Design Engineer — Asteralabs · San Jose, CA
• Principal Digital Design Engineer — Powerlattice · Chandler, AZ
• Senior Manager IP — Azuritypharmaceuticalsindia · Hyderabad, IN