Interconnect Design Engineer

About this role

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

Are you ready?  

To learn more about SiFive’s phenomenal success and to see why we have won the   GSA’s prestigious Most Respected Private Company Award   (for the fourth time!), check out our   website   and   Glassdoor   pages.

Job Description:   The Role: SiFive is looking for a junior hardware engineer who is passionate about designing industry-leading CPU and interconnect IP to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications. We’re creating massively customizable IP and improving time-to-market by designing hardware as highly-configurable generators. We leverage technology and ideas from the software industry to execute hardware design with the agility of software development.

We build and maintain multiple CPU lines, TileLink interconnects and other uncore/infrastructure IP using the Chisel hardware construction library embedded in the Scala language, and are seeking motivated individuals to enhance/evolve our existing IP as well as develop new IP. 

The Challenge • Designing the best interconnect IP in the world, based on the revolutionary open RISC-V and TileLink architectures

• Mastering the art of designing hardware as configurable generators in a domain-specific software language for elaborating circuits

• W orking in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance

Responsibilities • Architect, design and implement an enhanced TileLink interconnect, cache controllers, protocol bridges, and other infrastructure/uncore logic as RTL generators in Chisel

• Implement RTL generators such that elements self-configure to optimally connect to each other 

• Enhance future designs to provide higher performance, more efficient multi-core and multi-system coherence

• Design extensive configurability in as a first-class consideration

• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.

• Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans

• Ensure that knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design

What you bring to the challenge • Knowledge of cache and cache coherency architectures and concepts

• Experience with NoC or other interconnect fabrics

• Familiarity with industry-standard bus protocols (AXI, AHB, APB, CHI)

• Ability to architect solutions to connect bus fabrics of disparate protocols

• Strong software engineering skills/background, including: • Object-oriented, aspect-oriented, and particularly functional programming

• Templated metaprogramming, in any language

• Compiler infrastructures, particularly for domain-specific languages

• Data modeling, particularly intermediate representations for optimizing or transforming compiler passes

• Test-driven development, particularly ability to write adaptive unit tests

• Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL

• Attention to detail and a focus on high-quality design

• Ability to work well with others and a belief that engineering is a team sport

• BS/MS in EE, CE, CS or a related technical discipline, or equivalent experience

Nice to have • Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software

• Knowledge of RISC-V architecture

• Experience with Git/Github, Jira, Confluence

Pay & Benefits

Consistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. 

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.   The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range $139,752.00-$170,808.00 In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! 

Additional Information:

This position requires a successful background a

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