Entry Level ASIC/FPGA Design Engineer – Space Electronics - MTV

About this role

Entry Level ASIC/FPGA Design Engineer – Space Electronics - MTV

Company: The Boeing Company

Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple Entry Level ASIC/FPGA Design Engineers to join us as part of our Boeing Electronic Products team at the heart of Boeing’s products in Mountain View, CA.

From complex digitally beamformed phased arrays for constellation satellite programs to computing and networking equipment for commercial airplanes, the Boeing Electronic Products group develops ASICs and FPGAs that are at the heart of Boeing’s products!

We leverage leading-edge technology and work with world-class partners to provide some of the most complex SoCs in the world.  We develop robust, high-performance custom processors using the latest ARM IP to enable high-integrity, low SWAP-C flight computers. We apply the latest digital IC design processes with industry-best tools to enable applications which cut across every domain.

Our diverse development portfolio provides opportunities to learn with exposure to the breadth of the Boeing product line – approximately half our design work is within the Space & Launch business unit, and half is from other parts of Boeing (AvionX; Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems).

As an ASIC/FPGA Engineer on the Boeing Electronic Products team you will develop state-of-the-art digital ICs/SoCs to support the most critical programs across the enterprise.  We’re hiring design and verification engineers at the entry and associate levels to support new and existing projects.  We collaborate with other electronics groups across the company and around the world and support ASIC/FPGA design and verification for electronics that we build in El Segundo or various other Boeing sites.

Position Responsibilities may include: • Develop FPGA/ASIC designs supporting design and/or verification teams

• Implement FPGA/ASIC with latest design practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs)

• Integrate DSP IP from Boeing’s algorithm team and third-party IP as needed

• Perform static timing analysis, LEC, CDC, linting, and other necessary checks to ensure the design is completed on schedule

• Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation

• Create self-checking and reusable test benches from scratch, applying Object Oriented Programming concepts such as Inheritance and Polymorphism, and leverage UVM to build agents consisting of drivers, sequencers, monitors, and use of predictors together with scoreboards for checking correctness

• Support FPGA-based prototyping and validation depending on program and system requirements and complexity

• Validate design through hardware integration test with special test equipment, test-beds, and higher-level systems as needed

•

This position is expected to be 100% onsite.  The selected candidate will be required to work onsite at the listed location.

Basic Qualifications (Required Skills/Experience): • This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.

• Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement

• Coursework, Projects, or internship experience with ASIC/FPGA design or verification

• Familiarity with Register Transfer Language - e.g. Verilog, VHDL, SystemVerilog

Preferred Qualifications (Desired Skills/Experience): • Bachelor’s Degree in Electrical Engineering or Computer Engineering

• Experience with hardware emulators, especially Palladium

• Proficiency with hardware verification languages: System Verilog, System Verilog Assertions

• Ability to executable test plans

• Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.

• Ability to create self-checking and reusable testbenches from scratch

• Experience developing Functional Coverage Models and Closing Code Coverage

• Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)

• Proficient in scripting languages: Make, Perl, Python, etc.

• Revision Control Systems: svn, cvs, git

• Proficient in Linux Environments

• Familiarity with space-based design techniques and radiation mitigation

• Demonstrated history of 1st pass success with ASIC designs

Conflict of Interest: Successful candidate for this job must satisfy the Company’s Conflict of Interest (COI) assessment process.

Typical Education/Experience:   Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics, or chemistry (e.g. Bachelor), or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

Relocation: This position offers relocation based on candidate eligibility. Note: Basic relocation will be offered for eligible internal candidates.

Drug Free Workplace: Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies .

Shift Work: This position is for 1st shift.

Total Rewards: At Boeing, we strive to deliver a Total Rewards package that will attract, engage and retain the top talent. Elements of the Total Rewards package include competitive base pay and variable compensation oppor

Similar jobs

• Principal Engineer - FPGA/ASIC Design — Rolls-Royce · Washington D.C. RRNA Headquarters
• Principal ASIC Design Engineer — Hewlett Packard Enterprise · Sunnyvale, California, United States
• Staff FPGA Design Engineer — Terranorbitalcorporation · Irvine, CA
• Senior FPGA Design Engineer — Anellophotonics · Santa Clara, CA
• Staff Engineer, ASIC/VLSI Synthesis and Design — Marvell · San Diego, CA
• ASIC / FPGA Digital Design Engineer – (Associate or Experienced) — Boeing · USA - El Segundo, CA | USA - Huntington Beach, CA
• FPGA/ASIC Design Engineer (Silicon Engineering) — Spacex · Redmond, WA
• Verification Engineering Manager (ASIC & FPGA) — Boeing · USA - El Segundo, CA | USA - Huntington Beach, CA