Distinguished Engineer (Chiplet Lead - Photonic Fabric)

About this role

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. The Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.

The Photonic Fabric™ includes optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.

This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. What You Can Expect Marvell Technology is seeking a highly experienced  Chip Lead  to own the  end ‑ to ‑ end development of a heterogeneous photonic chiplet  comprising a  high ‑ speed electrical IC with advanced analog SERDES  and a  photonic integrated circuit (PIC) , brought together using  advanced co ‑ packaged technologies . 

This role requires technical breadth across  mixed ‑ signal SoC design, photonic integration, chiplet ‑ style partitioning, firmware and package ‑ level co ‑ design , along with proven leadership delivering complex silicon from concept through  silicon bring ‑ up, ATE, and system validation . 

The ideal candidate has shipped  high ‑ speed I/O and/or optical products , understands electrical‑optical tradeoffs, and can act as the single technical owner across die, package, optics, and system boundaries. 

Key Responsibilities   • Own the  end ‑ to ‑ end product design  spanning Electrical IC, Photonic IC, firmware stack, and advanced packaging design. 

• Lead  micro ‑ architecture and RTL development  for the Electrical IC that can include high speed SERDES and digital subsystems with internally developed IPs and industry standard external IPs such as UALink, UCIe, etc. 

• Collaborate with verification team to ensure robust functional and performance verification spanning digital RTL, AMS and electrical-optical interfaces. 

• Work closely with physical design and packaging teams on floorplanning, physical implementation, timing, power, and physical verification closure. 

• Partner with DFT experts to  drive  DFT strategy  for digital, analog SERDES, and system‑level testability. 

• Partner with photonics team to define  PIC architecture , interfaces, and control schemes, and ensure robust  electrical-optical co ‑ design.  

• Collaborate with test engineering to drive  ATE enablement , test program development, and debug. 

• Lead cross-functional team to complete  system ‑ level validation , including boards, optics, firmware, and software interaction. Drive root‑cause analysis across silicon, package, optics, and system domains. Mentor and develop senior engineers and influence cross functional teams across disciplines in a matrixed environment. 

• Identify and communicate technical status, risks, and tradeoffs to engineering and product leadership. 

What We're Looking For • Bachelor’s degree in Computer Science, Electrical Engineering, or related fields and 15+ years of related professional experience OR Master’s degree / PhD in Computer Science, Electrical Engineering or related fields with 8-12 years of experience. 

• 15+ years of experience in  ASIC / SoC development  with  end ‑ to ‑ end chip ownership . 

• Strong experience across Micro‑architecture and RTL design, high‑speed  analog SERDES , physical design and sign‑off, DFT and manufacturing test, advanced packaging and chiplet‑style integration, post‑silicon bring‑up, ATE, and system validation. 

• Ability to  clearly articulate architectural and implementation tradeoffs  across performance, power, area, yield, cost, schedule, and risk.  

• Strong track record of  driving alignment  across cross‑functional teams with differing viewpoints in a matrixed environment and drive solutions to tough engineering problems across the product stack. 

• Excellent written and verbal communication skills, including leading technical reviews and communicating status, risks, and decisions to engineering and product leadership at the executive level. 

• While deep expertise across all domains is not expected, the ideal candidate will demonstrate the maturity and technical judgment to foster a culture of cross-domain collaboration and deal with conflicts in a calm and constructive fashion. 

​ Preferred Qualifications   • Prior experience in delivery of  high ‑ speed I/O and/or optical products  into production. 

• Prior experience as  Chip Lead, SoC Architect, or System ‑ Level Technical Lead . 

Expected Base Pay Range (USD) 209,770 - 314,300, $ per annum The successful candidate’s starting base pay will be deter

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