Design Verification Engineer

About this role

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Job Description:

The CSG group at Broadcom has brought some of the most complex and cutting edge networking ASIC's and multichip solutions to market over the last decade. The group develops Tomahawk ASICs for Scale-Out and Scale-Up AI Networks. These products support the latest networking protocols and features as well as manage extremely large volumes of traffic of the order of several hundreds of Terabits/sec. These networking ASIC's support a large number of ports ranging from 10/100Mb/s to 1600Gb/s speeds as well as various line interfaces and protocols.

The successful candidate will be responsible for various key tasks in the areas of verification of cutting edge network switch routing designs. The daytoday tasks for this position include but are not limited to the following: 1) Participating in the verification processes of L2/L3 Network Switching and routing ASICs and various subsystems within these chips 2) Understanding the architecture and implementation of these chips and coming up with in depth test plans for verifying various key networking features such as L2/L3 traffic streaming, traffic management, scheduling and shaping of traffic, latency and performance characterization of chips and systems. 3) Developing verification environments including testbenches and verification API’s associated with the chip architecture to enable testing of various features within the chips as well as scripts and Makefiles as required to run the environment in various tool chains 4) Implementing test plans into executable test suites using a cutting edge Systemverilog verification environment. 5) Executing the verification process to completion pre-silicon using various functional and code coverage metrics as measures of completion

The successful candidate will satisfy the following requirements: 1) MSEE or BSEE or equivalent, with concentration in digital design and excellent academic standing. Total engineering minimum experience required is typically a BS degree and 8+ years of experience, an MS degree and 6+ years of experience or a PhD and 3+ years of experience or equivalent. 2) Familiar with Hardware description languages (Verilog/SystemVerilog/UVM), scripting languages (Perl, Python) and Object Oriented Programming (OOP). 3) Exposure to cutting edge verification and validation techniques and methodologies using Object Oriented modular reusable environments in languages such as Systemverilog, Perl, Python 4) Strong understand and prior experience of end-to-end verification process from test plan definition to coverage closure on ASIC/SOC silicon that has gone into mass production 5) Excellent verbal and written communication skills.

Additional Job Description: Compensation and Benefits The annual base salary range for this position is  $120,000  - $192,000   As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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